1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a line-on-glass type liquid crystal display device that prevents a deterioration in a picture quality of the liquid crystal display device.
2. Description of the Related Art
A liquid crystal display device controls the light transmittance of liquid crystal having dielectric anisotropy by using an electric field, thereby displaying a picture. Further, the liquid crystal display device includes a liquid crystal display panel having liquid crystal cells arranged in a matrix shape and a drive circuit for driving the liquid crystal display panel. The liquid crystal display panel controls the light transmittance of the cells in accordance with a pixel signal, thereby displaying a picture.
In addition, the drive circuit includes a gate driver for driving gate lines of the liquid crystal display panel, a data driver for driving data lines, a timing controller for controlling the drive timing of the gate driver and the data driver, and a power supply for supplying power signals required for driving the liquid crystal display panel and the drive circuits.
Further, the data and gate drivers are divided into a plurality of integrated circuits (ICs) made in a chip form. Each of the integrated drive ICs is mounted in an IC area opened on a TCP (tape carrier package) or is mounted on a base film of the TCP by a COF (chip on film) method. Each IC is also electrically connected to the liquid crystal display panel by a TAB (tape automated bonding) method. Further, the drive IC can also be directly mounted on the liquid crystal display panel by a COG (chip on glass) method.
The drive ICs mounted on the liquid crystal display panel by the COG method receive pixel data and control signals from the timing controller mounted on a main PCB (power control board) and power signals from the power supply through line-on-glass (LOG) type signal lines which are formed in the liquid crystal display panel and a corresponding FPC (flexible printed circuit).
Recently, even when the drive ICs are connected to the liquid crystal display panel through the TCP, the PCB is removed by adopting the LOG signal lines, thereby making the liquid crystal display device thinner. That is, the gate PCB which transmits relatively less signals is removed, and the signal lines which supply gate control signals and power signals to the gate drive ICs are formed in the LOG type lines on the liquid crystal display panel. Accordingly, the gate drive ICs mounted on the TCP receive the gate control signals from the timing controller and the power signals from the power supply through the following arrangement: main PCB→FPC->data PCB->data TCP->LOG signal line->gate TCP.
In more detail, FIG. 1 is a diagram representing an LOG type liquid crystal display device of the related art where a gate PCB is removed. As shown, the LOG type liquid crystal display device includes a main PCB 20 having a timing controller 22 and a power supply 24, a data PCB 16 connected to the main PCB 20 through a FPC 18, a data TCP 12 where a data drive IC 14 is mounted and which is connected between the data PCB 16 and a liquid crystal display panel 6, and a gate TCP 8 where a gate drive IC 10 is mounted and which is connected to the liquid crystal display panel 6.
Further, the liquid crystal display panel 6 is divided into a thin film transistor array substrate 2 and a color filter array substrate 4, which are bonded with a liquid crystal there between. Also, liquid crystal cells independently driven by the thin film transistors are respectively provided at each area defined by the crossing of gate lines GL and data lines DL of the thin film transistor array substrate 2. Each thin film transistor supplies a pixel signal from the data line DL to the liquid crystal cell in response to a scan signal from the gate line GL.
In addition, the data drive ICs 14 are connected to the data lines DL through a data pad of the liquid crystal display panel 6 and the data TCP 12, thereby supplying a data signal to the data line DL. Similarly, the gate drive ICs 10 are connected to the gate lines GL through a gate pad of the liquid crystal display panel 6 and the gate TCP 8, thereby supplying a gate signal to the gate line GL.
A LOG signal line group 26 include signal lines for power signals from the power supply 24 such as a gate low voltage, gate high voltage, common voltage, etc, and gate control signals supplied from the timing controller 22. On the other hand, as shown in FIG. 2, in an edge area of the color filter array substrate 4, a plurality of silver Ag dots 30a to 30d are formed to supply a common voltage to the common electrode formed in the color filter array substrate 4. That is, a common voltage VCOM from the common line LVCOM is supplied to the common electrode of the color filter array substrate 4 through the silver dots 30a and 30b. 
However, as shown, the silver dots 30a to 30d are located in corner areas of the color filter array substrate 4. That is, in the related art, the part that supplies the common voltage VCOM is insufficient (e.g., too small of an area), therefore a picture quality deterioration phenomenon such as cross-talk, a greenish color, etc. is generated.